Memory mapped I/O interfacing with 8085 microprocessor
In memory mapped I/O interfacing with 8085 microprocessor, the I/O devices are not given separate addresses other than treated as a memory location. Whose address range between 0000h to FFFFh (64k).But some part of the space is reserved for I/O devices. The advantage is any instruction that references memory can also transfer data between an I/O device and the microprocessor, as long as the I/O port is assigned to the memory address space rather than to the I/O address space. The register associated with the I/O port is simply treated as memory location register.
Now we can discuss this memory mapped I/O interfacing with 8085 microprocessor with an example in which address bit A15 designates whether instructions reference memory or an I/O device. If A15= 0, a memory register is addressed; If A15= 1, than a memory mapped I/O device is address .this assignment elevates the first 32k bytes of memory address space to memory and second 32k to memory mapped I/O devices. External logic generates devices select pulses for memory mapped I/O only when = 0, the appropriate address is on the address low and a or strobe occurs.
Input and output transfer using memory mapped I/O are not limited to the accumulator. For example, same of 8085 A instructions that can be used for input from memory mapped I/O ports.
MOV r, m :- Move the connects of input port whose address is available in (H,L) reg pair to any internal register.
LDA addr :- Load the acc with the content of the input port whose address is available as a second and third byte of the instruction.
Other instructions include, ANA M, ADD M, M provide input data transfer and computation in a single instruction. same instruction that out the data from memory mapped ports are
MVI M, data
LHLD and SHLD carry out 16- bit I/O transfers with single instructions which reduce program executive time considerably. The price paid for this added capability is a reduction in directly addressable main memory and the necessity of decoding a 16- bit rather than an 8-bit address.
Now we discuss the process of memory mapped I/O interfacing with 8085 microprocessor by which microprocessor work in Memory mapped I/O interfacing with 8085 microprocessor. When a microprocessor puts out an address and generates a control strobe for a memory read, it has no way of determining whether the device that responds with data is a memory device or an I/O device. It only requires that the devices that respond with in the allowable access time or uses the READY line to request a sufficient number of WAIT states. It supplies an address data and a write strobe and continues its operations, external logic determines whether memory, I/O or anything at all receives the data transferred.
Memory address decoding is nothing but to assign an address for each location in the memory chip. The data stored in the memory is accessed by specifying its address. Memory address can be decoded in two ways:
- Absolute or Fully decoding and
- Linear Select or Partial decoding
There are many advantages in absolute address decoding.
- Each memory location has only one address, there is no duplication in the address
- Memory can be placed contiguously in the address space of the microprocessor
- Future expansion can be made easily without disturbing the existing circuitry
There are few disadvantages in this method
- Extra decoders are necessary
- Some delay will be produced by these extra decoders.
The main advantage of linear select decoding is its simplified decoding circuit. This reduces the hardware design cost. But there are many disadvantages in this decoding.
- Multiple addresses are provided for the same location
- Complete memory space of the microprocessor is not efficiently used
- Adding or interfacing ICs with already existing circuitry is difficult.
Absolute Address Decoding: The 8085 microprocessor has 16 address lines. Therefore it can access 216 locations in the physical memory. If all these lines are connected to a single memory device, it will decode these 16 address lines internally and produces 216 different addresses from 0000H to FFFFH so that each location in the memory will have a unique address.
74LS138 address decoder to generate the chip select signals for each memory block. In this decoder when the address lines A13, A14 and A15 are 000, the output line Y0 will be activated as shown in Fig. This in turn selects the first memory block. Similarly when these lines are 001 (C=0, B=0 and A=1) Y1 will be activated and the second memory block will be selected.
In this type of memory interfacing, all the address lines (A0 to A15) have been used. Each location in the memory will have a single address. This type of address decoding is called as absolute or fully decoded addressing.
According to the value of Ao and A1, any one register will be selected and to select one memory chip we need one chip select signal CS signal as shown in the next diagram.