Parallel in parallel out shift register
We already discussed on a) serial in serial out shift register b) serial in parallel out shift register c) parallel in serial out shift register. Now in this post we will see fourth type of register, parallel in parallel out shift register, which is designed such that data can be shifted into or out of the register in parallel.
As we discuss earlier that parallel in means the input data will enter in parallel so at a time to all flip flop. We now can develop an idea for the parallel entry of data into the register. Here the data bits are entered into the flip flops simultaneously, rather than a bit-by-bit basis. Let take an example suppose we have to save a 4-bit number (1011). Then all input are feed the inputs of different 4 number of flip flop. With single clock pulse all data are enter to all 4 flip flops. Another very important thing in this type of register there is no interconnection between the flip flops since no serial shifting is required. Hence, the moment the parallel entry of the data is accomplished the data will be available at the parallel outputs of the register. A simple parallel in parallel out shift register is shown below.
From this above diagram we can see the parallel inputs to be applied at A, B, C, and D inputs are directly connected to the D inputs of the respective flip flops. On applying the clock transitions, these inputs are entered into the register and are immediately available at the outputs Q1, Q2, Q3, and Q4.