Peripheral mapped I/O interfacing

In peripheral mapped I/O interfacing, the I/O devices are treated differently from memory chips. In this method the control signals I/O read ( IOR ) and I/O write ( IOW), which are derived from the IO/M, RD and WR signals of the 8085, are used to activate input and output devices, respectively.

Now question is how this control signal generated? Generation of these control signals is shown in Fig. bellow. Table shows the status of IO/M, RD and WR signals during I/O read and I/O write operation.

Peripheral mapped I/O interfacing

In peripheral mapped I/O interfacing, IN instruction is used to access input device and OUT instruction is used to access output device. Each I/O device is identified by a unique 8-bit address assigned to it. Since the control signals used to access input and output devices are different, and all I/O device use 8-bit address, a maximum of 256 (28) input devices and 256 output devices can be interfaced with 8085.

Peripheral mapped I/O interfacing

Now it will be better for us if we discuss the topic with an example. In bellow we take an example and discussed to show how peripheral mapped I/O interfacing work.

Ex: Interface an 8-bit DIP switch with the 8085 such that the address assigned to the DIP switch if F0H.

As per our above discussion we know that in peripheral mapped I/O interfacing, IN instruction is used to get data from DIP switch and store it in accumulator. Steps involved in the execution of this instruction are:

  1. Address F0H is placed in the lines A0 – A7 and a copy of it in lines A8 – A15.
  2. The IOR signal is activated ( IOR = 0), which makes the selected input device to place its data in the data bus.

iii. The data in the data bus is read and store in the accumulator.

Fig. shows the interfacing of DIP switch.

A7        A6        A5        A4        A3         A2          A1       A0

1            1           1          1            0           0             0           0 = F0H

A0 – A7 lines are connected to a NAND gate decoder such that the output of NAND gate is

The output of NAND gate is ORed with the IOR signal and the output of OR gate is connected to 1G and 2G of the 74LS244. When 74LS244 is enabled, data from the DIP switch is placed on the data bus of the 8085. The 8085 read data and store in the accumulator. Thus data from DIP switch is transferred to the accumulator

Peripheral mapped I/O interfacing

Hope this discussion on peripheral mapped I/O interfacing clear your concept.

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