In my previous post I discussed on asynchronous counter. Now this post you will find what is a synchronous counter?
If we think on the timing delay to perform an operation of counter then we will find each flip-flop has a specific delay time. In ripple counters these delay times are additive and the total “settling” time for the counter is approximately the product of the delay time of a single flip-flop and the total number of flip-flops.
Now if we want to overcome this problem we need something to do. And the solution is if all the flip-flops are clocked synchronously then we can easily overcome the problem. If all the flip-flops of a counter are clocked synchronously then this is known as a synchronous counter. Synchronous counters can be designed for any count sequence (need not be straight binary). In bellow picture is shown of a simple 4-bit synchronous counter.
The above picture is shows A 4-bit synchronous counter with parallel carry. In carefully look that the clock inputs of all the flip-flops are tied together so that the input clock signal may be applied simultaneously to each flip-flop. As we see all flip-flops are T flip-flop and it work on toggle mode when T input is 1. That is why only the LSB flip-flop A has its T input connected permanently to logic 1 (i.e., VCC), while the T inputs of the other flip-flops are driven by some combination of flip-flop outputs. The T input of flip-flop B is connected to the output QA of flip-flop A; the T input of flip-flop C is connected with the AND-operated output of QA and QB. Similarly, the T input of D flip-flop is connected with the AND-operated output of QA, QB, and QC.
As we know a T flip-flop changes its state with the negative transition of each clock pulse for T is high. Flip-flop B changes its state only when the value of QA is 1 and a negative transition of the clock pulse takes place. Similarly, flip-flop C changes its state only when both QA and QB are 1 and a negative edge transition of the clock pulse takes place. In the same manner, the flip-flop D changes its state when QA = QB = QC = 1 and when there is a negative transition at clock input. The count sequence of the counter is given in Table