Interrupt Driven I/O Data Transfer

Here we see how interrupt driven I/O data transfer work. In my previous post I discussed on programmed I/O data transfer method. And we saw that in the programmed I/O data transfer method, microprocessor is busy all the time in checking for the availability of data from the slower I/O devices. And it also busy in checking if I/O device is ready for the data transfer or not. In other words in this data transfer scheme, some of the microprocessor time is wasted in waiting while an I/O device is getting ready. To overcome this problem interrupt driven I/O data transfer introduced.

 The interrupt driven I/O data transfer method is very efficient because no microprocessor time is wasted in waiting for an I/O device to be ready. In this interrupt driven I/O data transfer method the I/O device informs the microprocessor for the data transfer whenever the I/O device is ready. This is achieved by interrupting the microprocessor. As we know that the interrupt is hardware facilities provided on the microprocessor.

interrupt driven I/O data transfer

  Now come to the working process of interrupt driven I/O data transfer. So the beginning the microprocessor initiates data transfer by requesting the I/O device ‘to get ready’ and then continue executing its original program rather wasting its time by checking the status of I/O device. Whenever the device is ready to accept or supply data, it informs the processor through a control signal. This control signal known as interrupt (INTR) signal. In response to this interrupt signal, the microprocessor sends back an interrupt acknowledge signal to the I/O device. By sending acknowledgement it indicating that it received the request. It then suspends its job after executing the current instruction. It saves the contents and status of program counter to stack and jumps to the subroutine program.

 This subroutine program is called Interrupt Service Subroutine (ISS) program. The ISS saves the processor status into stack; and after executing the instruction for the data transfer, it restores the processor status and then returns to main program.

As already discussed, several input/output devices may be connected to microprocessor using Interrupt Driven Data Transfer Scheme. Following interrupt request configuration may arise while interfacing the I/O devices to microprocessor.

  1. Single Interrupt system
  2. Multi Interrupt System

Single Interrupt System

When only one interrupt line is available with the microprocessor and several I/O devices are to be connected, then the method is known as Single Interrupt System.

Multi Interrupt System

When the microprocessor has several interrupt terminals and one I/O device is to be connected to each interrupt terminal, then it is known as multi interrupt system. In this scheme, the number of I/O devices to be connected to the interrupt lines should be equal to or less than the number of interrupt terminals. In this way one device is connected to each level of interrupt. So when a device interrupts the microprocessor, it immediately knows which device has interrupted. Such an interrupt scheme is known as vectored interrupt.

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