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Pin configuration of 8085 microprocessor

As we know 8085 microprocessor is a 40 pin IC. It is very important to know the pin configuration of 8085 microprocessor, before study the 8085 microprocessor programming. In bellow you can see the pin configuration of 8085 microprocessor in figure.

Pin Diagram

Pin configuration of 8085 microprocessor

X1 & X2 (Pin 1 and 2):

These X1 and X2 pins are also called Crystal Input Pins. 8085 microprocessor can generate clock signals internally.  To generate internal clock signals, 8085 microprocessor requires external inputs from X1 and X2 pins.

RESET IN and RESET OUT (Pin 36 and Pin 3) :

RESET IN:

This pin is used for hard resting the microprocessor. It works on active low signal. When the signal on this pin is low for at least 3 clocking cycles, it forces the microprocessor to hard reset itself. Resetting the microprocessor means,

  • Firstly, It Clears the PC and IR.
  • Secondly, Disabling all interrupts (except TRAP).
  • Thirdly, Disabling the SOD pin.
  • Fourthly, All the buses (data, address, control) are tri-stated.
  • Finally, Gives HIGH output to RESET OUT pin.
RESET OUT:

RESET OUT is used to reset the peripheral devices and other ICs present on the circuit. It is an output signal. It works on active high signal. The output on this pin goes high whenever RESET IN is given low signal. The output remains high as long as RESET IN is kept low.

SID and SOD (Pin 4 and Pin 5):

SID (Serial Input Data):

It takes 1 bit input from serial port of 8085 microprocessor. SID stores the bit at the 8th position (MSB) of the Accumulator.  RIM (Read Interrupt Mask) instruction used for transfer the bit.

SOD (Serial Output Data):

SOD takes 1 bit from Accumulator to serial port of 8085. It takes the bit from the 8th position (MSB) of the Accumulator. SIM (Set Interrupt Mask) instruction is used to transfer the bit.

TRAP (Pin 6):

TRAP is a non-maskable interrupt. As we know, it has the highest priority. It cannot be disabled and TRAP has highest priority among the all hardware interrupt. It is both edge and level triggered. That means TRAP signal must go from low to high. And must remain high for a certain period of time. TRAP usually used for power failure and emergency shutoff.

RST 7.5 (Pin 7 (Input)):

RST 7.5 is a maskable interrupt. It has the second highest priority. It is positive edge triggered only. The internal flip-flop is triggered by the rising edge. The flip-flop remains high until it cleared by RESET IN.

RST 6.5 (Pin 8):

RST 6.5 is a maskable interrupt. It has the third highest priority. It is level triggered only. The pin has to goes high for a specific period of time. RST 6.5 usually enabled by EI instruction. It usually disabled by DI Instruction

RST 5.5 (Pin 9):

RST 5.5 is a maskable interrupt. It has the fourth highest priority. It also level triggered device. The pin has to goes high for a specific period of time. This interrupt is very similar to RST 6.5.

INTR (Pin 10 (Input)):

INTR is a maskable interrupt. It has the lowest priority. And INTR also level triggered device. It is a general purpose interrupt. By general purpose we mean that it can used at vector microprocessor to any specific subroutine having any address.

INTA (Pin 11 (Output)):

INTA stands for interrupt acknowledge. It is an outgoing signal. It is an active low signal. Low output on this pin indicates that microprocessor has acknowledged the INTR request.

AD0 – AD7 (Pin 19-12 (Bidirectional)):

These pins serve the dual purpose of transmitting lower order address and data byte. During 1st clock cycle, these pins act as lower half of address. In remaining clock cycles, these pins act as data bus. The separation of lower order address and data done by address latch.

A8 – A15 (Pin 21-28 (Unidirectional)):

These pins carry the higher order of address bus. The address sent from microprocessor to memory. These 8 pins switched to high impedance state during HOLD and RESET mode.

ALE (Pin 30 (Output)):

It used to enable Address Latch. It indicates whether bus functions as address bus or data bus. If ALE = 1 then, Bus functions as address bus. If ALE = 0 then, Bus functions as data bus.

S0 and S1 (Pin 29 (Output) and Pin 33 (Output)):

S0 and S1 both called Status Pins. They tell the current operation which is in progress in 8085.

IO/M (Pin 34 (Output)):

This pin tells whether I/O or memory operation is being performed.

If IO/M = 1 then, I/O operation is being performed. If IO/M = 0 then, Memory operation is being performed. The operation being performed is indicated by S0 and S1.

If S0 = 0 and S1 = 1 then, It indicates WRITE operation. If IO/M = 0 then, It indicates Memory operation. Combining these two we get Memory Write Operation. In bellow table shown the relation of IO/M with S0 and S1.

Pin configuration of 8085 microprocessor

RD (Pin 32 (Output)):

RD stands for Read. It is an active low signal. It is a control signal used for Read operation either from memory or from Input device. A low signal indicates that data on the data bus must be placed either from selected memory location or from input device.

WR (Pin 31 (Output)):

WR stands for Write. It is also active low signal. It is a control signal used for Write operation either into memory or into output device. A low signal indicates that data on the data bus must be written into selected memory location or into output device.

READY (Pin 35 (Input)):

This pin used for synchronize slower peripheral devices with fast microprocessor. A low value causes the microprocessor to enter into wait state. The microprocessor remains in wait state until the input at this pin goes high.

HOLD (Pin 38 (Input)):

HOLD pin mainly used to request the microprocessor for DMA transfer. A high signal on this pin is a request to microprocessor to relinquish the hold on buses. This request come form DMA controller. Intel 8257 and Intel 8237 are two DMA controllers.

HLDA (Pin 39 (Output)):

HLDA stands for Hold Acknowledge. The microprocessor uses this pin to acknowledge the receipt of HOLD signal. When HLDA signal goes high, address bus, data bus, RD, WR, IO/M pins become tri-stated. This means they are cut-off from external environment. The control of these buses goes to DMA Controller. Control remains at DMA Controller until HOLD become high. When HOLD goes low, HLDA also goes low and the microprocessor takes control of the busses.

VSS and VCC (Pin 20 (Input) and Pin 40 (Input)):

+5V power supply connected to VCC . Ground signal connected to VSS.

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Subham

Subham

Hi myself Subham Dutta, having 15+ years experience in filed of Engineering. I love to teach and try to build foundation of students. Try to make them imagine what they learn.

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