From the name Serial in Serial out Shift Register (SISO), it is obvious that this type of register accepts data serially, one bit at a time at the single input line, and shifted to next flip flop serially. The output is also obtained on a single output line in a same serial fashion. Now depending upon the data shift within the register, it may be shifted from left to right using shift-left register, or may be shifted from right to left using shift-right register.
As I mansion earlier in my post what is a shift register? That the basic unit of a register is a flip flop. So a shift right register can be constructed with either J-K or D flip flops as shown in bellow.
As we can see in above figure that J-K flip flop based shift register requires connection of both J and K inputs. Input data are connected to the J and K inputs of the left most (lowest order) flip flop of flip flop chain. And all flip flops are connected in serially. As we know that for a JK flip flop output is followed whatever the input of J and the both the input are complimentary. Let take an example to input a 0, one should apply a 0 at the J input, i.e., J = 0 and K = 1 and vice versa. With the application of a clock pulse the data will be shifted by one bit to the right. In this way the first data will store at Flip flop A then in next clock pulse the date of A flip flop is shifted to filp flop B in that way finally we get the serial output from flip flop D.
For example, consider that all the stages are reset and a logical input 1011 is applied at the serial input line connected to stage A. and see the bellow table that how the data shifted from one flip flop to other and finally get the output from D flip flop.
After fourth clock pulse we will get first input after next three clock pulse the complete input (1011) which we feed at flip flop A will out from flip flop D. Now in bellow see the waveform of 4 bit serial shift register.
Shift Left Register
For Shift Left Register the reverse action takes place. In that case input is feed from right side and output is getting from left side. See the block diagram of Shift Left Register in bellow.
Hope the above discussion clear your concept on Serial in Serial out Shift Register (SISO).