The development of A/D converters has progressed in a quest to reduce the conversion time. The successive approximation type ADC aims at approximating the analogue signal to be digitized by trying only one bit at a time.
As we discussed on counter type adc and flash type adc on my early post but work process of Successive Approximation Type ADC is different. The process of A/D conversion by this technique can be illustrated with the help of an example. Let us take a four-bit successive approximation type ADC.
Initially, the counter is reset to all 0s. The conversion process begins with the MSB being set by the start pulse. That is, the flip-flop representing the MSB is set. The counter output is converted into an equivalent analogue signal and then compared with the analogue signal to be digitized. A decision is then taken as to whether the MSB is to be left in (i.e. the flip-flop representing the MSB is to remain set) or whether it is to be taken out (i.e. the flip-flop is to be reset) when the first clock pulse sets the second MSB. Once the second MSB is set, again a comparison is made and a decision taken as to whether or not the second MSB is to remain set when the subsequent clock pulse sets the third MSB.
The process continues until we go down to the LSB. Note that, every time we make a comparison, we tend to narrow down the difference between the analogue signal to be digitized and the analogue signal representing the counter count. Refer to the operational diagram of Fig. 12.33. It is clear from the diagram that, to reach any count from 0000 to 1111, the converter requires four clock cycles. In general, the number of clock cycles required for each conversion will be n for an n-bit A/D converter of this type.
The above Fig -1 shows a block schematic representation of a successive approximation type ADC. Since only one flip-flop (in the counter) is operated upon at one time, a ring counter, which is nothing but a circulating register (a serial shift register with the outputs Q and Q of the last flip-flop connected to the J and K inputs respectively of the first flip-flop), is used to do the job. Referring to Fig – 2, the dark lines show the sequence in which the counter arrives at the desired count, assuming that 1001 is the desired count. This type of A/D converter is much faster than the counter-type A/D converter previously discussed. In an n-bit converter, the counter-type A/D converter on average would require 2n−1 clock cycles for each conversion, whereas a successive approximation type converter requires only n clock cycles. That is, an eight-bit A/D converter of this type operating on a 1 MHz clock has a conversion time of 8 s.