Timing diagram of 8085 microprocessor
To know the working of 8085 microprocessor, we should know the timing diagram of 8085 microprocessor. With help of timing diagram we can easily calculate the execution time of instruction as well as program. Before go for timing diagram of 8085 microprocessor we should know some basic parameters to draw timing diagram of 8085 microprocessor. Those parameters are
- Instruction Cycle
- Machine cycle
Now we should go for what is instruction cycle, machine cycle and t-state?
Instruction cycle is the total time taken for completing one instruction execution
Machine cycle is the time required to complete one operation such as accessing either the memory or an I/O device
T-state is the time corresponding to one clock period. It is a basic unit used to calculate the time taken for execution of instructions and programs in a processor.
Now another important topics we should know to clear the concept on timing diagram of 8085 microprocessor. What are the control signals used in timing diagram of 8085 microprocessor?
If we go for above question then the answer is mainly we have to know five control signal to understand timing diagram of 8085 microprocessor. Those are
IO/ M signal indicate whether I/O or memory operation is being carried out. A high on this signal indicates I/O operation while a low indicates memory operation.
S0 and S1
S0 and S1 indicate the type of machine cycle in progress.
ALE is indicates the availability of a valid address on the multiplexed address/data lines. When it is high act as a address bus and low act as a data bus.
Read is an active low signal that indicates that data is to be read form the selected memory or i/o device through data bus.
Write is an active low signal that indicates that data on the data bus is to be write form the selected memory or i/o device.
In bellow table I show the status of different control signal for different operation. We should remember that to complete our timing diagram of 8085 microprocessor.
Now in bellow diagram see the opcode fetch timing diagram.
The lower byte of address (AD0 – AD7) is available on the multiplexed address/data bus during T1 state of each machine cycle, except during the bus idle machine cycle.
The higher byte of address (A8 – A15) is available during T1 to T3 states of each machine cycle, except during the bus idle machine cycle, shown in Fig
The first machine cycle of every instruction is the Opcode Fetch. This indicates the kind of instruction to be executed by the system. The length of this machine cycle varies between 4T to 6T states—it depends on the type of instruction. In this, the processor places the contents of the PC on the address lines, identifies the nature of machine cycle æ (by IO/M, S0, S1) and activates the ALE signal. All these occur in T1 State In T2 state, RD signal is activated so that the identified memory location is read from and places the content on the data bus (D0 – D7 ).
In T3, data on the data bus is put into the instruction register (IR) and also raises the RD^ signal thereby disabling the memory.
In T4, the processor takes the decision, on the basis of decoding the IR, whether to enter into T5 and T6 or to enter T1 of the next machine cycle.
One byte instructions that operate on eight bit data are executed in T4. Examples are ADD B, MOV C, B, RRC, DCR C,etc.
Now see an example of memory read and memory write machine cycle.
Both the Memory Read and Memory Write machine cycles are 3T states in length. In Memory Read the contents of R/W memory (including stack also) or ROM are read while in Memory Write, it stores data into data memory.
As is evident from Fig during T2 and T3 states data from either memory or CPU are made available in Memory Read or Memory Write machine cycles respectively. The status signal (IO/ M, S0, S1) states are complementary in nature in Memory Read and Memory Write cycles. Reading or writing operations are performed in T2.
In T3 of Memory Read, data from data bus are placed into the specified register (A,B, C, etc.) and raises RD so that memory is disabled while in T3 of Memory Write WR^ signal is raised which disables the memory.