Parallel in serial out shift register (PISO)

In our previous post we discussed on Serial in parallel out shift register (SIPO) now in this post we will focus on Parallel in serial out shift register (PISO).

As name suggests the input data will enter in parallel that means at a time to all flip flop. And output will get serially. We now can develop an idea for the parallel entry of data into the register. Here the data bits are entered into the flip flops simultaneously, rather than a bit-by-bit basis. Let take an example suppose we have to save a 4-bit number (1011). Then all input are feed the inputs of different 4 number of flip flop. With single clock pulse all data are enter to all 4 flip flops. In bellow see the block diagram of 4 bit of parallel in serial out shift register.

Now from above 4 bit parallel in serial out shift register we can see, A, B, C, and D are the four parallel data input lines and SHIFT / LOAD (SH / LD) is a control input that allows the four bits of data at A, B, C, and D inputs to enter into the register in parallel or shift the data in serial. When SHIFT / LOAD is HIGH, AND gates G1, G3, and G5 are enabled, allowing the data bits to shift right from one stage to the next. When SHIFT / LOAD is LOW, AND gates G2, G4, and G6 are enabled, allowing the data bits at the parallel inputs. When a clock pulse is applied, the flip-flops with D = 1 will be set and the flip-flops with

D = 0 will be reset, thereby storing all the four bits simultaneously. The OR gates allow either the normal shifting operation or the parallel data-entry operation, depending on which of the AND gates are enabled by the level on the SHIFT / LOAD input.