Serial in Parallel out Register (SIPO)
As we see in my previous post that construction and working principle of serial in serial out register (SISO). Now we see the construction and working principle of serial in parallel out register (SIPO).
In serial in parallel out register (SIPO), the input data is entering and shifted in serially, but output taken in parallel. So question is how to obtain the output data in parallel? For that it is required that all the output bits are available at the same time. And we can get this parallel output by connecting the output of each flip flop to an output pin. Once the data is stored in the flip flop the bits are available simultaneously. Now let take an example of 8-bit serial in parallel out register (IC74164) and see its logic diagram and pin diagram in bellow.
As it is 8-bit so it has eight S-R flip-flops, which are all sensitive to negative clock transitions. Now from above diagram we can see
(1) Each flip-flop has an asynchronous CLEAR input;
(2) The true side of each flip-flop is available as an output
So all those 8 bits of any number stored in the register are available simultaneously as an output. And we can get that outputs simultaneously from every flip flop parallel-ly.
Another important pin available here for clearing the register and when we apply low label to pin 9 of IC74164 all flip flops are reset.
Here we see two inputs A and B. Suppose that the serial data is connected to B; then A can be used as a control line. Now if A getting high then the input data shifted serially. And if A getting low then the output of Nand gate will be zero. So only zero to enter in register.