Asynchronous 3-bit up down counter

Here we come with asynchronous 3-bit up down counter. Some questions we have to clear during the post.

• What is up counter?
• What is down counter?
• How can we combined both?
• How Asynchronous 3-bit up down counter construct?
• Working Principal

What is up counter?

Lets start with UP-Counter. As name suggest it start counting from 0,1,2,3,4,5,6,7,8,9. Every steps it count upper value from lower. In my previous post on ripple counter we already saw the working principle of up-counter. I request you please read that to complete discussion.

What is down counter?

So now time to see the circuit diagram. Looks at bellow and mind it, only the outputs of the counter may be taken from the complement outputs of the flip-flops, i.e., Q′, rather than from the normal outputs for each flip-flop as shown in circuit 

Since the outputs are taken from the complements of the flip-flops. The starting count sequence is Q′₂Q′₁Q′₀ = 111. With each negative edge of the clock Q₀ toggles its state. Similarly, with each negative transition of the output Q₀, the output Q₁ toggles and the same thing happens for Q₂, also. Hence the count sequences goes on decreasing from 7, 6, 5, 4, 3, 2, 1, 0, 7, and so on with each clock pulse. 

How can we combined both?

Now we have to do some smart work. We have to make it by combine both Up-Counter and Down Counter. For that we have to go through some process. Now question is how can we do that? We place both counter’s truth table then combine them. And make a new truth table for that. And from new truth table, we have to design new circuit by karnaugh Map technique.  

How Asynchronous 3-bit up down counter construct?

As we know that in the up-counter each flip-flop is triggered by the normal output of the preceding flip-flop (from output Q of first flip-flop to clock of next flip-flop); whereas in a down-counter, each flip-flop is triggered by the complement output of the preceding flip-flop (from output Q^ of first flip-flop to clock of next flip-flop).

Working Principal

The operation of such a counter is controlled by the up-down control input. Now question is in which sequence it will count see below the table for the counting sequence of the it in the two modes of counting.

 As I discussed earlier that for up down counting operation preceding flip-flop sometime it need input from output from output Q of first flip-flop to clock of next flip-flop for up-counting and sometimes from output Q^ of first flip-flop to clock of next flip-flop for down-counting. So in above circuit diagram it is shown clearly. As we know a flip-flop can hold single bit so for 3 bit operation it need three flip-flops. An inverter has been inserted in between the count-up control line and the count-down control line to ensure that the count-up and count-down cannot be simultaneously in the HIGH state.

When the count-up/down line is held HIGH, the lower AND gates will be disabled and their outputs will be zero. So they will not affect the outputs of the OR gates. At the same time the upper AND gates will be enabled. Hence, QA will pass through the OR gate and into the clock input of the B flip-flop. Similarly, QB will be gated into the clock input of the C flip-flop. Thus, as the input pulses are applied, it will count up and follow a natural binary counting sequence from 000 to 111.

Similarly, with count-up/down line being logic 0, the upper AND gates will become disabled and the lower AND gates are enabled, allowing Q′A and Q′B to pass through the clock inputs of the following flip-flops. Hence, in this condition the counter will count in down mode, as the input pulses are applied.

Let Check How you learn counter? with simple quiz.