RS flip flop

RS flip flop is a basic flip flop where R stands for reset and S stands for set. So S-R flip flop we can call Set-Reset flip flop. Now if you have clear idea on how a flip-flop works then it is very easy to understand the working principle of RS flip flop and for that you may follow my previous post what is a flip-flop.

  So start with RS flip flop we should know that the a RS flip flop made with a R-S latch and triggering circuit. A flip flop can work with 1) negative triggering 2) positive triggering. In bellow you will see a NAND gate implementation of an RS flip-flop with active high inputs with truth table.

 R-S flip-flop

 

The two NAND gates are cross-coupled. That is, the output of NAND 1 is fed back to one of the inputs of NAND 2, and the output of NAND 2 is fed back to one of the inputs of NAND 1. The remaining inputs of NAND 1 and NAND 2 are the S and R inputs. The outputs of NAND 1 and NAND 2 are respectively Q and Q outputs.

 

Now point to be remembering for RS flip flop.

 

  1. SET=RESET= 1 is forbidden as such a condition tries to set (that is, Q = 1 ) and reset (that is, Q = 1) the flip-flop at the same time. To be more precise, SET and RESET inputs in the RS flip flop cannot be active at the same time.

 

  1. SET = 0 and RESET = 1 sets the flip-flop. Q and Q^ respectively go to the ‘0’ and ‘1’ state.

 

  1. SET =1 and RESET =0 resets or clears the flip-flop. Q and Q^ respectively go to the ‘1’ and ‘0’ state.

 

  1. SET = RESET = 0 is the normal resting condition of the flip-flop. It has no effect on the output state of the flip-flop. Both Q and Q outputs remain in the logic state they were in prior to this input condition.

 

The above circuit of RS flip flop is also referred to as an R-S latch. This is because any combination at the inputs immediately manifests itself at the output as per the truth table. Now only difference between a latch and flip-flop is that a flip-flop is clock trigger. The outputs change states as per the inputs only on the occurrence of a clock pulse. The clocked flip-flop could be a level-triggered one or an edge-triggered one. In bellow see the circuit diagram of RS flip flop with truth table.

R-S flip-flop

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