Now in this post we can discuss on ripple counter. As we know from my previous post regarding what is a counter? Now we start with simplest ripple counter circuit which can be built using T flip flops because as we know T flip flop is operate only toggle mode of JK Flip flop. So we can easily use it for counting the input pulse of flip flop. Instead of T flip flop we can also use JK flip flops with the toggle property in hand.
Introduction
The main property of a ripple counter has in this counter all the flip flops are not driven by the same clock pulse. Here the clock pulse is applied to the first flip flop. And the successive flip flop is triggered by the output of the previous flip flop. So by this property it is very much clear that ripple counter has cumulative settling time, which limits its speed of operation.
As the first stage of the counter changes its state first with the application of the clock pulse to the flip flop and the successive flip flops change their states in turn causing a ripple through effect of the clock pluses. As the signal propagates through the counter in a ripple fashion, it is called a ripple counter.in bellow you will find the block diagram of 3-bit ripple counter.
Block Diagram
By 3-bit ripple counter we can count 0-7. Because we know by 3 bit we can represents minimum 0 (000) and maximum 7 (111). The clock inputs of the three flip flops are connected in cascade. The T input of each flip flop is connected to a constant 1, which means that the state of the flip flop will toggle at each negative edge of its clock. Thus the clock input of the first flip flop is connected to the Clock line. The other two flip flops have their clock inputs driven by the Q output of the preceding flip flop. Therefore, they toggle their state whenever the preceding flip flop changes its state from Q = 1 to Q = 0, which results in a negative edge of the Q signal. So as we take the output from Q0,Q1,Q2 then we get the count sequence with different counter state as mention bellow on table.
Counting Sequence
Here we see counting sequence of ripple counter. The sequence of binary states that the flip-flops will follow as clock pulses which applied continuously. In bellow diagram shows how it count 0-7. An n-bit binary counter repeats the counting sequence for every 2n (n = number of flip-flops) clock pulses and has discrete states from 0 to 2n–1. 
Timing Diagram of Ripple Counter
Another very important thing we should know when we study ripple counter that the timing diagrams for it. Here in bellow you will see the timing diagram of three bit ripple counter. As we know that here ripple counter has three stages, each comprising of a single flip-flop. Only the first stage responds directly to the Clock signal. Hence we may say that this stage defiantly synchronized to the clock.
The other two stages respond after an additional delay. For example, when count = 3, the next clock pulse will change the count to 4. Now this change requires all three flip-flops to toggle their states. The change in Q0 observed only after a propagation delay from the negative edge of the clock pulse. The Q1 and Q2 flip-flops have not changed their states yet. Hence, for a brief period, the count will be Q2Q1Q0 = 010. The change in Q1 appears after a second propagation delay, and at that point the count is Q2Q1Q0 = 000. Finally, the change in Q2 occurs after a third delay. Hence the stable state of the circuit reaches and the count is Q2Q1Q0 = 100. The timing diagram indicates that the counting sequence is 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, and so on. This circuit is a modulo-8 counter. Since it counts in the upward direction, we call the circuit an up-counter.
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